CISC and RISC instructions and their handling

CISC and RISC instructions and their handling
The first CPU's had a so called Complex Instruction Set Computer (CISC). This means that the
computer can understand many and complex instructions. The X86 instruction set, with its
varying length from 8 to 120 bit, was originally developed for the 8086 with its mere 29000
transistors.
Reduced Instruction Set Computer (RISC): The RISC instructions are brief and the same length
(for example 32 bit long, as in Pentium Pro), and they process much faster than CISC
instructions. Therefore, RISC is used in all newer CPU's. However, the problem is that the
instructions arrive at the CPU in 8086 format. Thus, they must be decoded
For every new CPU generation, the instruction set has been expanded. The 386 came with 26
new instructions, the 486 with 6 new instructions, and Pentium with 8 new instructions. These
changes mean that some programs require at least a 386 or a Pentium processor to work.
There is also a continuous optimizing of the instruction handling process. One is that the clock
frequency increases, as we will see later - the faster, the better. But what can the CPU do in
one clock tick. That is critical to its performance. For example, a 386 needed 6 clock ticks to
add a number to a sub total. A job which the 486 manages in only two clock ticks, because of
more effective instruction decoding, 5th and 6th generation CPU's can execute more than one
of those operations in one clock tick, since they contain more processing lines (pipelines),
which work parallel.